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FEATURES Low Cost 3.3 V CMOS MxFETM for MCNS-DOCSIS, DVB-, DAVIC-Compliant Set-Top Box and Cable Modem Applications 232 MHz Quadrature Digital Upconverter 12-Bit Direct IF DAC (TxDAC+(R)) Up to 65 MHz Carrier Frequency DDS Programmable Sampling Clock Rates Selectable Interpolation Filter Analog Tx Output Level Adjust 12-Bit, 33 MSPS Direct IF ADC Dual 8-Bit, 16.5 MSPS Sampling IQ ADCs Two 12-Bit - Auxiliary DACs Direct Interface to AD8321/AD8325 or AD8322/AD8327 PGA Cable Driver APPLICATIONS Cable Modems Set-Top Boxes Wireless Modems GENERAL DESCRIPTION
Tx DATA
Mixed-Signal Front End Set-Top Box, Cable Modem AD9877
FUNCTIONAL BLOCK DIAGRAM
COS Tx INTERPOLATOR FILTER DDS SIN 12 CONTROL FUNCTIONS 2 8 RxIQ DATA Rx 8 ADC Q IN ADC 12 SDELTA0 SDELTA1 OSCOUT I IN 12 DAC 3 Tx CA
PLL SPORT PROFILE 4
12 RxIF DATA ADC IF IN
AD9877
The AD9877 is a single-supply cable modem/set-top box mixed-signal front end. The device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and a transmit DAC. The receive path contains a 12-bit ADC and dual 8-bit ADCs. All internally required clocks and an output system clock are generated by the PLL from a single crystal or clock input. The transmit path interpolation filter provides upsampling factors of 12 or 16 with an output signal bandwidth as high as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required.
The 12-bit ADC has excellent undersampling performance, allowing it to deliver better than 10 ENOBs with IF inputs up to 70 MHz. The 12-bit IF ADC can sample at a rate up to 33 MHz, allowing it to process wideband signal inputs. Two programmable sigma-delta DACs are available and can be used to control external components, such as variable gain amplifiers (VGAs) or voltage-controlled tuners. The AD9877 integrates a CA port that enables a host processor to control the AD8321/AD8325 or AD8322/AD8327 programmable gain amplifier (PGA) cable drivers via the MxFE SPORT. The AD9877 is available in a 100-lead MQFP package. It offers enhanced receive path undersampling performance and lower cost, compared to the pin-compatible AD9873. The AD9877 is specified over the extended industrial (-40oC to +85oC) temperature range.
MxFE is a trademark of Analog Devices, Inc. TxDAC+ is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
5%, AD9877-SPECIFICATIONS (V = 3.3 V PLL (f V f = 54 MHz (M = 8 and N = 4). ADC sample frequencies derived from
AS MCLK
3.3 V 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, ), RSET = 4.02 k , max. fine gain, 75 DAC load.) MCLK
Test Level II II II II III III N/A II II III III III III III III II I I I II II II II III III III N/A II N/A 3 35
DS =
Parameter SYSTEM CLOCK DAC SAMPLING, fSYSCLK Frequency Range (N = 4) Frequency Range (N = 3) OSCIN and XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Impedance MCLK JITTER Cycle to Cycle (fMCLK derived from PLL) Tx DAC CHARACTERISTICS Resolution Full-Scale Output Current Gain Error (using internal reference) Offset Error Reference Voltage (REFIO Level) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ 1 kHz Offset, 42 MHz Carrier Output Voltage Compliance Range Wideband SFDR 5 MHz Analog Out, IOUT = 10 mA 65 MHz Analog Out, IOUT = 10 mA Narrow-Band SFDR ( 1 MHz Window): 65 MHz Analog Out, IOUT = 10 mA Tx MODULATOR CHARACTERISTICS I/Q Offset Pass-Band Amplitude Ripple (f < fIQCLK/8) Pass-Band Amplitude Ripple (f < fIQCLK/4) Stop-Band Response (f > fIQCLK x 3/4) Tx GAIN CONTROL Gain Step Size Gain Step Error Settling Time, 1% (Full-Scale Step) 8-BIT ADC CHARACTERISTICS Resolution Conversion Rate Pipeline Delay Offset Matching between I and Q ADCs Gain Matching between I and Q ADCs Analog Input Input Voltage Range Differential Input Impedance Full Power Bandwidth Input Referred Noise Dynamic Performance (AIN = -0.5 dBFS, f = 5 MHz) Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Reference Voltage Error REFT8-REFB8 (0.5 V)
Temp Full Full Full 25C 25C 25C N/A Full Full 25C 25C 25C 25C 25C 25C Full Full Full Full Full Full Full Full 25C 25C 25C N/A Full N/A
Min
Typ
Max 232 177 33 65
Unit MHz MHz MHz % M pF ps rms Bits mA %FS %FS V LSB LSB pF dBc/Hz V dBc dBc dBc dB dB dB dB dB dB s Bits MHz ADC Cycles LSBs LSBs Vppd k pF MHz V dB Bits dB dB mV
50 100 3 6 12 10 -1 1.0 1.23 2.5 8 5 -110
4 -2.5
20 +2.5
-0.5 48 48 53 50 55 51 69 55
+1.5
0.1 0.5 -63 0.5 0.05 1.8 8 16.5 3.5 8.0 2.0 1 42 90 600 40.8 6.5 52.0 -100 47.3 7.6 -60.1 63.0 10
Full 25C 25C 25C Full Full Full Full Full
II III III III I I I I I
-50.0
+100
-2-
REV. A
AD9877
Parameter 12-BIT ADC CHARACTERISTICS Resolution Conversion Rate Pipeline Delay Analog Input Input Voltage Range Differential Input Impedance Aperture Delay Aperture Uncertainty (Jitter) Full Power Bandwidth Input Referred Noise Reference Voltage Error REFT12-REFB12 (1 V) Dynamic Performance (AIN = -0.5 dBFS, f = 5 MHz) ADC Sample Clock = OSCIN Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOBs) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) ADC Sample Clock = PLL Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOBs) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Dynamic Performance (AIN = -0.5 dBFS, f = 50 MHz) ADC Sample Clock = OSCIN Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Differential Phase Differential Gain CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation (5 MHz Analog Output) Isolation between Tx and 8-Bit ADCs Isolation between Tx and 12-Bit ADCs ADC-to-ADC Isolation (AIN = -0.5 dBFS, f = 5 MHz) Isolation between I/Q in and IF12 Isolation between Q and I Inputs TIMING CHARACTERISTICS (10 pF Load) Wake-Up Time Minimum RESET Pulsewidth Low (tRL) Digital Output Rise/Fall Time Tx/Rx Interface MCLK Frequency (fMCLK) TxSYNC/TxIQ Setup Time (tSU) TxSYNC/TxIQ Hold Time (tHD) MCLK Rising Edge to RxSYNC/RxIQ/IF Valid Delay (tMD) OSCOUT Rising or Falling Edge to RxSYNC/ RxIQ/IF Valid Delay (tOD) OSCOUT Edge to MCLK Falling Edge (tEE) Temp N/A Full N/A Full 25C 25C 25C 25C 25C Full Test Level N/A II N/A III III III III III III I -200 Min Typ 12 33 5.5 2 4.2 2.0 1.2 85 75 16 65.9 10.7 66.2 -79.1 79.3 64.6 10.4 64.8 -78 79.3 +200 Max Unit Bits MHz ADC Cycles Vppd k, pF ns ps rms MHz V mV
Full Full Full Full Full Full Full Full Full Full
I I I I I II II II II II
63.2 10.2 63.7 72.5 62.0 10.0 62.5 72.5
-68.3
dB Bits dB dB dB dB Bits dB dB dB
-67.8
Full Full Full Full Full 25C 25C
II II II II II III III
61.1 9.9 61.5 69.9
63.1 10.2 63.3 -77 79.6 <0.1 <1
-67.9
dB Bits dB dB dB Degrees LSB
25C 25C
III III
80 90
dB dB
25C 25C N/A N/A Full Full Full Full Full Full Full
III III N/A N/A II II II II II II II
70 65 200 5 2.8 4 66 3 3 0 TOSC/4 - 2.0 -1.0 1.0 TOSC/4 + 3.0 +1.0
dB dB tMCLK Cycles tMCLK Cycles ns MHz ns ns ns ns ns
REV. A
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AD9877
SPECIFICATIONS (continued)
Parameter Serial Control Bus (continued) Maximum SCLK Frequency (fSCLK) Minimum Clock Pulsewidth High (tPWH) Minimum Clock Pulsewidth Low (tPWL) Maximum Clock Rise/Fall Time Minimum Data/Chip-Select Setup Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) CMOS LOGIC INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance CMOS LOGIC OUTPUTS (1 mA Load) Logic "1" Voltage Logic "0" Voltage POWER SUPPLY Supply Current, IS (Full Operation) Analog Supply Current IAS Digital Supply Current IDS Supply Current, IS Standby (PWRDN Pin Active) Full Power-Down (Register 02h = 0xF9) Power-Down Tx Path (Register 2 = 0x20) Power-Down Rx Paths (Register 2 = 0x19) Reset (RESET Pin Active) Power Supply Rejection (Differential Signal) Tx DAC 8-Bit ADC 12-Bit ADC
Specifications subject to change without notice.
Temp Full Full Full Full Full Full Full 25C 25C 25C 25C 25C 25C 25C 25oC 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C
Test Level II II II II II II II II II II II III II II II III III II III III III III III III III
Min
Typ
Max 15
Unit MHz ns ns s ns ns ns V V A A pF V V mA mA mA mA mA mA mA mA % FS % FS % FS
30 30 1 25 0 30 DRVDD - 0.7 0.4 12 12 3 DRVDD - 0.6 0.4 313 85 228 104 10 60 265 85 <0.25 <0.004 <0.0004 355
113
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AD9877
ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS
Power Supply (VAVDD, VDVDD, VDRVDD) . . . . . . . . . . . . 3.9 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Digital Inputs . . . . . . . . . . . . . . . -0.3 V to DRVDD + 0.3 V Analog Inputs . . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature . . . . . . . . . . . . . . . . . -40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300C
*Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
I
Devices are 100% production tested at 25C and guaranteed by design and characterization testing for industrial operating temperature range (-40C to +85C). Parameter is guaranteed by design and/or characterization testing. Parameter is a typical value only.
II III
N/A Test level definition is not applicable.
THERMAL CHARACTERISTICS Thermal Resistance
100-Lead MQFP JA = 40.5C/W
ORDERING GUIDE
Model
Temperature Range
Package Description 100-MQFP
Package Option S-100C
AD9877ABS -40C to +85C
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9877 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-5-
AD9877
PIN CONFIGURATION
REFT12 REFB12 REFT8 REFB8 AGND AGND AGND AGND AVDD AVDD AVDD AVDD AGND Q IN+ IF12- Q IN-
80 AGNDIQ 79 I IN+ 78 I IN- 77 AGNDIQ 76 NC 75 NC 74 AGNDIQ 73 AVDDIQ 72 DRVDD 71 OSCOUT 70 DRGND 69 DGNDSD 68 SDELTA0 67 SDELTA1 66 DVDDSD 65 CA_EN 64 CA_DATA 63 CA_CLK 62 DVDDOSC 61 OSCIN 60 XTAL 59 DGNDOSC 58 AGNDPLL 57 PLLFILT 56 AVDDPLL 55 DVDDPLL 54 DGNDPLL 53 AVDDTx 52 Tx+ 51 Tx- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
IF12+
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AVDD 1 DRGND 2 DRVDD 3 IF(11) 4 IF(10) 5 IF(9) 6 IF(8) 7 IF(7) 8 IF(6) 9 IF(5) 10 IF(4) 11 IF(3) 12 IF(2) 13 IF(1) 14 IF(0) 15 RxIQ(3) 16 RxIQ(2) 17 RxIQ(1) 18 RxIQ(0) 19 RxSYNC 20 DRGND 21 DRVDD 22 MCLK 23 DVDD 24 DGND 25 TxSYNC 26 TxIQ(5) 27 TxIQ(4) 28 TxIQ(3) 29 TxIQ(2) 30
NC
AD9877
TOP VIEW 100-Lead MQFP
DVDD
DVDD
NC
DVDDTx
SDIO
PROFILE(1)
PROFILE(0)
NC = NO CONNECT
-6-
AGNDTx
TxIQ(1)
TxIQ(0)
DGNDTx
PWRDN
RESET
FSADJ
DGND
DGND
DGND
CS
REFIO
SCLK
SDO
REV. A
AD9877
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 84, 87, 92, 95 2, 21, 70 3, 22, 72 25, 34, 39, 40 24, 33, 38 45 46 50 53 54 55 56 58 59 62 66 69 73 74, 77, 80 83, 88, 91, 96, 99 4:15 16:19 20 23
Mnemonic AVDD DRGND DRVDD DGND DVDD DGNDTx DVDDTx AGNDTx AVDDTx DGNDPLL DVDDPLL AVDDPLL AGNDPLL DGNDOSC DVDDOSC DVDDSD DGNDSD AVDDIQ AGNDIQ AGND
Pin Function 12-Bit ADC Analog 3.3 V Supply Pin Driver Digital Ground Pin Driver Digital 3.3 V Supply Digital Ground Digital 3.3 V Supply Tx Path Digital Ground Tx Path Digital 3.3 V Supply Tx Path Analog Ground Tx Path Analog 3.3 V Supply PLL Digital Ground PLL Digital 3.3 V Supply PLL Analog 3.3 V Supply PLL Analog Ground Oscillator Digital Ground Oscillator Digital 3.3 V Supply Sigma-Delta Digital 3.3 V Supply Sigma-Delta Digital Ground 8-Bit ADC Analog 3.3 V Supply 8-Bit ADC Analog Ground 12-Bit ADC Analog Ground
Pin No. 26 27:32 35, 36 37 41 42 43 44 47 48 49 51, 52 57 60 61 63 64 65 67 68 71 75, 76 78, 79 81, 82 85 86 89, 90 93 94 97, 98 100
Mnemonic TxSYNC TxIQ[5:0] PROFILE[1:0] RESET SCLK CS SDIO SDO PWRDN REFIO FSADJ Tx-, Tx+ PLLFILT XTAL OSCIN CA_CLK CA_DATA CA_EN SDELTA1 SDELTA0 OSCOUT NC I IN-, I IN+ Q IN-, Q IN+ REFB8 REFT8 NC REFB12 REFT12 IF12-, IF12+ NC
Pin Function Sync Input for Transmit Port Digital Input for Transmit Port Profile Selection Inputs Chip Reset Input SPORT Clock SPORT Chip Select SPORT Data I/O SPORT Data Output Power-Down Transmit Path TxDAC Decoupling (to AGND) DAC Output Adjust (External Res.) Tx Path Complementary Outputs PLL Loop Filter Connection Crystal Oscillator Inv. Output Oscillator Clock Input Serial Clock to Cable Driver Serial Data to Cable Driver Serial Enable to Cable Driver Sigma-Delta Output Stream 1 Sigma-Delta Output Stream 0 Oscillator Clock Output No Connect (Leave Floating) Differential Input to I ADC Differential Input to Q ADC 8-Bit ADC Decoupling Node 8-Bit ADC Decoupling Node No Connect (Leave Floating) 12-Bit ADC Decoupling Node 12-Bit ADC Decoupling Node Differential Input to IF ADC No Connect (Leave Floating)
IF[11:0] RxIQ[3:0] RxSYNC MCLK
12-Bit ADC Digital Output Muxed I and Q ADC Output Sync Output, IF, I, and Q ADCs Master Clock Output
REV. A
-7-
AD9877
DEFINITIONS OF SPECIFICATIONS APERTURE DELAY OFFSET ERROR
The aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion.
APERTURE UNCERTAINTY (JITTER)
First transition should occur for an analog value 1/2 LSB above -FS. Offset error is defined as the deviation of the actual transition from that point.
OUTPUT COMPLIANCE RANGE
Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC.
CHANNEL-TO-CHANNEL ISOLATION (CROSSTALK)
The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.
PHASE NOISE
In an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. The channel-to-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel.
DIFFERENTIAL NONLINEARITY ERROR (DNL, NO MISSING CODES)
An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1,024 codes, respectively, must be present over all operating ranges.
EFFECTIVE NUMBER OF BITS (ENOB)
Single sideband phase noise power is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly in single-tone transmit mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic.
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and the associated output data being made available.
POWER SUPPLY REJECTION
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula: N = (SINAD - 1.76 dB 6.02) It is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
GAIN ERROR
Power supply rejection specifies the converter's maximum full-scale change when the supplies are varied from nominal to minimum and maximum specified voltages.
SIGNAL-TO-NOISE AND DISTORTION (SINAD) RATIO
The first code transition should occur at an analog value one-half LSB above full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions.
INPUT REFERRED NOISE
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
The rms output noise is measured using histogram techniques. The ADC output code's standard deviation is calculated in LSB and converted to an equivalent voltage. This results in a noise figure that can be directly referred to the input of the MxFE.
INTEGRAL NONLINEARITY ERROR (INL)
The difference, in dB, between the rms amplitude of the DAC's output signal (or ADC's input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth unless otherwise noted).
TOTAL HARMONIC DISTORTION (THD)
Linearity error refers to the deviation of each individual code from a line drawn from the negative full scale through the positive full scale. The point used as the negative full scale occurs 1/2 LSB before the first code transition. The positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.
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AD9877
Table I. Register Map*
Address (Hex) 00 01 Bit 7 SDIO Bidirectional PLL Lock Detect Power-Down PLL Bit 6 LSB First SYSCLK Divider N = 3 (N = 4 Default) Power-Down DAC Tx Bit 5 RESET Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (Hex) 08 00 Type rw rw
OSCIN Multiplier M [4] MCLK Divider R [5:0]
02
Power-Down Power-Down Power-Down Digital Tx 12-Bit ADC 12-Bit ADC 0 Reference 0 0
0 0
Power-Down 8-Bit ADC
00
rw
03 04 05 06 07 08
Sigma-Delta Output [0] Control Word [3:0] LSB Flag [0]
Flag [0] Enable 00
rw rw rw rw rw Tx rw ADC
Sigma-Delta Output 0 Control Word [11:4] MSB 0 0 0
00
Flag [1] Enable 00
Sigma-Delta Output [0] Control Word [3:0] LSB Flag [1] 0 ADC Clock Select 0 0
Sigma-Delta Output 1 Control Word [11:4] MSB 0 0 0 0 0 0 0 0 0 0
00 00 80
Power-Down 0 RxSYNC and 8-Bit ADC CLOCK 0 0 0 1 0 0 0
09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0
0 0 0 Version [3:0]
0 0 0
00 00 00 10 00 00
rw r rw r rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx rw Tx
Tx Frequency Tuning Word Profile 3 LSBs [1:0] 0 0 0 0
Tx Frequency Tuning Word Profile 2 LSBs [1:0] 0 0
Tx Frequency Tuning Word Profile 1 LSB [1:0] DAC Gain Control [3:0] CA Interface Mode Select 0
Tx Frequency Tuning Word Profile 3 LSBs [1:0]
Profile Select [1:0]
Spectral Inversion Tx
Single-Tone Tx Mode
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Tx Frequency Turning Word Profile 0 [9:2] Tx Frequency Turning Word Profile 0 [17:10] Tx Frequency Turning Word Profile 0 [25:18] CA Interface Transmit Word Control Profile 0 [7:4] DAC Gain Control Profile 0 [3:0]
Tx Frequency Turning Word Profile 1 [9:2] Tx Frequency Turning Word Profile 1 [9:2] Tx Frequency Turning Word Profile 1 [9:2] CA Interface Transmit Word Control Profile 1 [7:4] DAC Gain Control Profile 1 [3:0]
Tx Frequency Turning Word Profile 2 [9:2] Tx Frequency Turning Word Profile 2 [9:2] Tx Frequency Turning Word Profile 2 [9:2] CA Interface Transmit Word Control Profile 2 [7:4] DAC Gain Control Profile 2 [3:0]
Tx Frequency Turning Word Profile 3 [9:2] Tx Frequency Turning Word Profile 3 [9:2] Tx Frequency Turning Word Profile 3 [9:2] CA Interface Transmit Word Control Profile 3 [7:4] DAC Gain Control Profile 3 [3:0]
*Register bits denoted with "0" must be programmed with a "0" every time that register is written.
REV. A
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3
AD9877
REGISTER BIT DEFINITIONS REGISTER 00--Initialization Bits 0 to 4: OSCIN Multiplier Bit 7: PLL Lock Detect
This register field is used to program the on-chip multiplier (PLL) that generates the chip's high frequency system clock fSYSCLK. For example, to multiply the external crystal clock fOSCIN by 16 decimals, program Register 0, Bits 4:0 as 0x10. The default value of M is 0x08. Valid entries range from M = 1-31. When M is chosen equal to 1, the PLL is disabled. All internal clocks are derived directly from OSCIN. The PLL requires 200 MCLK cycles to regain frequency lock after a change in M, the clock multiplier value. After the recapture time of the PLL, the frequency of fSYSCLK is stable. For timing integrity, certain restrictions on the values of M and N apply when both AD9877 transmit and receive paths are used. The supported modes are: ADC Clock Select 1, fOSCIN 0, fMCLK (PLL Derived)
Bit 5: RESET
When this bit is set low, the OSCOUT pin functions in its default mode and provides an output clock with frequency fMCKL/R as described above. If this bit is set to 1, the OSCOUT pin is configured to indicate whether the PLL is locked to fOSCIN. In this mode, the OSCOUT pin should be low-pass filtered with an RC filter of 1.0 k and 0.1 F. A high output on OSCOUT indicates the PLL has achieved lock with fOSCIN.
REGISTER 02--Power-Down
Sections of the chip that are not used can be powered down when the corresponding bits are set high. This register has a default value of 0x00; all sections active.
Bit 0: Power-Down 8-Bit ADC
Active high powers down the 8-bit ADC.
Bit 3: Power-Down 12-Bit ADC Reference
Active high powers down the 12-bit ADC reference. N 3 4 3 4 M 6 8 12 16
Bit 4: Power-Down 12-Bit ADC
Active high powers down the 12-bit ADC.
Bit 5: Power-Down Digital Tx
Active high powers down the digital transmit section of the chip, similar to the function of the PWRDN pin.
Bit 6: Power-Down DAC Tx
Active high powers down the DAC.
Bit 7: Power-Down PLL
Writing a 1 to this bit resets the registers to their default values and restarts the chip. The RESET Bit always reads back 0. The bits in Register 0 are not affected by this software reset. However, a low level at the RESET pin would force all registers, including all bits in Register 0, to their default state.
Bit 6: LSB First
Active high powers down the OSCIN multiplier.
REGISTER 03 to 06--Sigma-Delta Control Words
Active high indicates SPI serial port access of instruction byte and data registers is least significant bit (LSB) first. Default low indicates most significant bit (MSB) first format.
Bit 7: SDIO Bidirectional
The sigma-delta control words are 12 bits wide and split in MSB Bits [11:4] and LSB Bits [3:0]. Changes to the sigma-delta control words take effect immediately for every MSB or LSB register write. Sigma-delta output control words have a default value of "0." The control words are in straight binary format, with 0x000 corresponding to the bottom of the scale and 0xFFF corresponding to the top of the scale (see Figure 5 for details). If Flag Enable (Bit 0 of Register 3 or 5) is set high, the SDELTA pins will maintain a fixed logic level determined directly by the MSB of the sigma-delta control word.
REGISTER 08--ADC Clock Configuration Bit 4: Power-Down RxSYNC and 8-Bit ADC Clock
Active high configures serial port as a three-signal port with the SDIO pin used as a bidirectional input/output pin. Default low indicates the serial port uses four signals with SDIO configured as an input and SDO configured as an output.
REGISTER 01--Clock Configuration Bits 0 to 5: MCLK Divider
This register determines the output clock on the OSCOUT pin. At default zero (R = 0), OSCOUT provides a buffered version of the OSCIN clock signal for other chips. The register can also be used to divide the chip's master clock, fMCLK, by R, where R is an integer between 2 and 63. The generated reference clock on the OSCOUT pin can be used for external frequency controlled devices.
Bit 6: SYSCLK Divider
Setting this bit to 1 powers down the 8-bit ADC's sampling clock and stops the RxSYNC output pin. It can be used for additional power-saving on top of the power-down selections in Register 2.
Bit 7: ADC Clock Select
The OSCIN multiplier output clock, fSYSCLK, can be divided by 4 or 3 to generate the chip's master clock. Active high indicates a divide ratio of N = 3. Default low configures a divide ratio of N = 4.
When set high, the input clock at OSCIN is used directly as the ADC sampling clock. When set low, the internally generated master clock, MCLK, is used as the ADC sampling clock. Best ADC performance is achieved when the ADCs are sampled directly from fOSCIN using an external crystal or low jitter crystal oscillator.
REGISTER 0C--Die Revision Bits 0 to 3: Version
The die version of the chip can be read from this register.
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AD9877
REGISTER 0D--Tx Frequency Tuning Words LSBs
This register accommodates two least significant bits for each of the four frequency tuning words (see description of Burst Parameter below).
REGISTER 0E--DAC Gain Control
The 26-bit FTW is spread over four register addresses. Bit 25 is the MSB and Bit 0 is the LSB. The carrier frequency equation is given as:
fC = FTW x fSYSCLK
[
]
226
This register allows the user to program the DAC gain if Tx Gain Control Select Bit 3 in Register F is set to 0. Bits [3:0] 0000 0001 0010 0011 ... 1110 1111 DAC Gain 0.0 dB (Default) 0.5 dB 1.0 dB 1.5 dB ... 7.0 dB 7.5 dB
where fSYSCLK = M
fOSCIN and FTW < 0x2000000.
Changes to FTW bytes take effect immediately.
Cable Driver Gain Control
The AD9877 has a three-pin interface to the AD832x family of programmable gain cable driver amplifiers. This allows direct control of the cable driver's gain through the AD9877. In its default mode, the complete 8-bit register value is transmitted over the 3-wire CA interface. If Bit 3 of Register F is set high, Bits [7:4] determine the 8-bit word sent over the CA interface according to the table below. Bits [7:4] 0000 0001 0010 0011 0100 0101 0110 0111 1000 CA Interface Transmit Word 0000 0000 (Default) 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000
REGISTER 0F--Tx Path Configuration Bit 0: Single-Tone Tx Mode
Active high configures the AD9877 for single-tone applications (e.g., FSK). The AD9877 will supply a single frequency output as determined by the frequency tuning word selected by the active profile. In this mode, the TxIQ input data pins are ignored but should be tied to a valid logic voltage level. Default value is 0 (inactive).
Bit 1: Spectral Inversion Tx
When set to 1, inverted modulation is performed.
MODULATOR _ OUT = I cos (t ) + Q sin (t )
[
]
Default is logic zero, noninverted modulation.
MODULATOR _ OUT = I cos (t ) - Q sin (t )
[
]
In this mode, the lower bits determine the fine gain setting of the DAC output. Bits [3:0] 0000 0001 0010 0011 ... 1110 1111 DAC Fine Gain 0.0 dB (Default) 0.5 dB 1.0 dB 1.5 dB ... 7.0 dB 7.5 dB
Bit 3: CA Interface Mode Select
This bit changes the manner in which transmit gain control is performed. Typically, either AD8321/AD8325 (default 0) or AD8322/AD8327 (default 1) variable gain cable amplifiers are programmed over the chip's 3-wire cable amplifier (CA) interface. The Tx gain control select changes the interpretation of the bits in Registers 13, 17, 1B, and 1F (see Cable Driver Gain Control section).
Bit 4 and 5: Profile Select
The AD9877 quadrature digital upconverter is capable of storing four preconfigured modulation modes called profiles. Each profile defines a transmit frequency tuning word and cable driver amplifier gain (/DAC gain) setting. Profile Select [1:0] Bits or PROFILE [1:0] pins program the current register profile to be used. Profile Select bits should always be "0" if PROFILE[1:0] pins are used to switch between profiles. Using the Profile Select Bits as a means of switching between different profiles requires the PROFILE [1:0] pins to be tied low.
REGISTERS 10 through 1F: Burst Parameter Tx Frequency Tuning Words
New data is automatically sent over the 3-wire CA interface (and DAC gain adjust) whenever the value of the active gain control register changes or a new profile is selected. The default value is 0x00 (lowest gain). The formula for the combined output level calculation of the AD9877 fine gain and the AD8327 or AD8322 coarse gain is:
V8327 = V9877(0) + ( fine) 2 + 6(coarse) - 19
V8322 = V9877(0) + ( fine) 2 + 6(coarse) - 14
where fine = the decimal value of Bits [3:0]. coarse = the decimal value of Bits [7:8]. V9877(0): the level at AD9877 output in dBmV for fine = 0. V8327: the level at output of the AD8327 in dBmV. V8322: the level at output of the AD8322 in dBmV.
The frequency tuning word (FTW) determines the DDS-generated carrier frequency (fC) and is formed via a concatenation of register addresses.
REV. A
-11-
(VAS = 3.3 V, VDS = 3.3 V, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8 and N = 4). ADC sample rate derived directly from fOSCIN, RSET = 4.02 k (IOUT = 10 mA), and 75 DAC load, unless otherwise noted.)
TYPICAL POWER CONSUMPTION CHARACTERISTICS (Transmitted 20 MHz single tone, unless otherwise noted.)
340 320 300 300 280
POWER
AD9877-Typical Performance Characteristics
310
290 POWER 140 160 180 200 220 240
260 240
280
270 220 200 180 120 260
250 0 10 20 30
fSYSCLK - MHz
50 60 40 % DUTY CYCLE
70
80
90
100
TPC 1. Power Consumption vs. Clock Speed, fSYSCLK
TPC 2. Power Consumption vs. Transmit Burst Duty Cycle
DUAL SIDEBAND TRANSMIT SPECTRUM (see Table II for Dual-Tone Generation)
0 -10 -20 MAGNITUDE - dB 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 55
MAGNITUDE - dB
-30 -40 -50 -60 -70 -80 -90 0 2 4 6 10 12 14 8 FREQUENCY - MHz 16 18 20
57
59
61
65 67 69 63 FREQUENCY - MHz
71
73
75
TPC 3. Dual Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz, RSET = 4.02 k , DAC Gain = 7.5 dB, RBW = 1 kHz
SINGLE SIDEBAND TRANSMIT SPECTRUM
0 -10 -20
TPC 4. Dual Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz, RSET = 4.02 k (IOUT = 10 mA), RBW = 1 kHz
0 -10 -20
MAGNITUDE - dB
MAGNITUDE - dB
-30 -40 -50 -60 -70 -80 -90 0 10 20 30 50 60 70 40 FREQUENCY - MHz 80 90 100 110
-30 -40 -50 -60 -70 -80 -90 0 10 20 30 50 60 70 40 FREQUENCY - MHz 80 90 100 110
TPC 5. Single Sideband @ 65 MHz, RBW = 2 kHz, fC = 66 MHz, f = 1 MHz, RSET = 4.02 k , DAC Gain = 7.5 dB
TPC 6. Single Sideband @ 42 MHz, RBW = 2 kHz, fC = 43 MHz, f = 1 MHz, RSET = 4.02 k , DAC Gain = 7.5 dB
-12-
REV. A
AD9877
0 -10 -20
MAGNITUDE - dB
0 -10 -20
-30 -40 -50 -60 -70 -80 -90 0 10 20 30 50 60 70 40 FREQUENCY - MHz 80 90 100 110
MAGNITUDE - dB
-30 -40 -50 -60 -70 -80 -90 62.5 63.0
63.5 64.0
64.5 65.0 65.5 66.0 FREQUENCY - MHz
66.5 67.0
67.5
TPC 7. Single Sideband @ 5 MHz, RBW = 2 kHz, fC = 6 MHz, f = 1 MHz, RSET = 4.02 k , DAC Gain = 7.5 dB
TPC 8. Single Sideband @ 65 MHz, RBW = 500 Hz, fC = 66 MHz, f = 1 MHz, RSET = 4.02 k , DAC Gain = 7.5 dB
70
90
65
fOSCIN
85
fOSCIN
60
80
dB
dB
PLL
55
75
50
70
PLL
45
65
40 5 15 25 35 45 65 55 fIN - MHz 75 85 95 105
60 5 15 25 35 45 55 65 75 85 95 105
fIN - MHz
TPC 9. 12-Bit ADC SNR vs. Input Frequency
TPC 10. 12-Bit ADC SFDR vs. Input Frequency
11.0 10.5 10.0 9.5 9.0
ENOB
dB
-60
fOSCIN
-65
-70 PLL -75
8.5 8.0 PLL 7.5 7.0 6.5 6.0 5 15 25 35 45 55 65 fIN - MHz 75 85 95 105
-80
fOSCIN
-85
-90 5 15 25 35 45 55 65 75 85 95 105
fIN - MHz
TPC 11. 12-Bit ADC ENOBs vs. Input Frequency
TPC 12. 12-Bit ADC THD vs. Input Frequency
REV. A
-13-
AD9877
THEORY OF OPERATION
To gain a general understanding of the AD9877, it is helpful to refer to Figure 1, which displays a block diagram of the device architecture. The following is a general description of the device functionality. Later sections will detail each of the data path building blocks.
Transmit Section Modulation Mode Operation
The data assembler receives the multiplexed IQ data and creates two parallel 12-bit paths with I and Q data pairs, which comprise a complex symbol. The rate at which the I and Q data word pairs appear at the output of the data assembler will be referred to as the IQ sample rate (fIQCLK). Because four 6-bit reads are required at the TxIQ input to read a full 24-bit complex symbol, f MCLK is 4 times the IQ sample rate (fMCLK = 4 fIQCLK). Once through the data assembler, the IQ data streams are fed through two half-band filters (half-band filters #1 and #2). The combination of these two filters results in the sample rate increasing by a factor of 4. Thus, at the output of half-band filter #2, the sample rate is 4 fIQCLK. In addition to the sample rate increase, the half-band filters provide the low-pass filtering characteristic necessary to suppress the spectral images produced by the upsampling process.
The AD9877 accepts 6-bit words that are strobed synchronous to the master clock, MCLK, into the data assembler. A high level on TxSYNC signals the start of a transmit symbol. Two successive 6-bit words form a 12-bit symbol component. The incoming data is assumed to be complex, in that alternating 12-bit words are regarded as the in-phase (I) and quadrature (Q) components of a symbol. Symbol components are assumed to be in two's complement format. The rate at which the TxIQ data is read will be referred to as the master clock rate (fMCLK).
DATA ASSEMBLER 12 TxIQ 6 I
HALF-BAND FILTER #1
12
HALF-BAND FILTER #2
12
CIC FILTER
QUADRATURE MODULATOR COS 12 DAC
FSADJ
DAC GAIN CONTROL Tx
TxSYNC
Q
12
12
12 SIN DDS 2 2 N = 3, 4 R N OSCIN 12 (fSYSCLK ) (fOSCIN )
(fMCLK )
(fIQCLK )
MCLK REF CLK R = 2, 3, ..., 63
OSCIN MULTIPLIER
M
XTAL
M = 1, 2, ..., 31
3 2 4
CONTROL WORD 0 AD832x CTRL 8 BURST PROFILE CTRL SERIAL INTERFACE CONTROL WORD 1 2 (fOSCIN ) ADC
-
SDELTA0
12
-
SDELTA1
2
I INPUT
RxIQ
4 RxIQ DATA
MUX
REF8 ADC 2 (fOSCIN ) Q INPUT
RxSYNC
Rx IF
12
ADC
IF12 INPUT
AD9877
REF12
Figure 1. Block Diagram
-14-
REV. A
AD9877
After passing through the half-band filter stages, the IQ data streams are fed to a cascaded integrator-comb (CIC) filter. This filter is configured as an interpolating filter, which allows further upsampling rates of 3 or 4. The CIC filter, like the half-bands, has a built-in low-pass characteristic. Again, this provides for suppression of the spectral images produced by the upsampling process. The digital quadrature modulator stage following the CIC filters is used to frequency shift (upconvert) the baseband spectrum of the incoming data stream up to the desired carrier frequency. The carrier frequency is controlled numerically by a direct digital synthesizer (DDS). The DDS uses the internal system clock (fSYSCLK) to generate the desired carrier frequency with a high degree of precision. The carrier is applied to the I and Q multipliers in quadrature fashion (90 phase offset) and summed to yield a data stream that is the modulated carrier. It should be noted at this point that the incoming data has been converted from an input sample rate of fMCLK to an output sample rate of fSYSCLK (see Figure 1). The modulated carrier becomes the 12-bit samples sent to the DAC.
Single-Tone Output Transmit Operation OSCIN Clock Multiplier
As mentioned earlier, the output data is sampled at the rate of fSYSCLK. The AD9877 has a built-in programmable clock multiplier and an oscillator circuit. This allows the use of a relatively low frequency, thus less expensive, crystal or oscillator to generate the OSCIN signal. The low frequency OSCIN signal can then be multiplied in frequency by an integer factor of between 1 and 31, inclusive, to become the fSYSCLK clock. For DDS applications, the carrier is typically limited to about 30% of fSYSCLK. For a 65 MHz carrier, the system clock required is above 216 MHz. The OSCIN multiplier function maintains clock integrity as evidenced by the AD9877's excellent phase noise characteristics and low clock-related spur in the output spectrum. External loop filter components consisting of a series resistor (1.3 k) and capacitor (0.01 F) provide the compensation zero for the OSCIN multiplier PLL loop. The overall loop performance has been optimized for these component values.
Receive Section
The AD9877 can be configured for frequency synthesis applications by writing the single-tone bit true. In single-tone mode, the AD9877 disengages the modulator and preceding data path logic to output a spectrally pure single frequency sine wave. The AD9877 provides for a 26-bit frequency tuning word, which results in a tuning resolution of 3.2 Hz at a fSYSCLK rate of 216 MHz. A good rule of thumb when using the AD9877 as a frequency synthesizer is to limit the fundamental output frequency to 30% of fSYSCLK . This avoids generating aliases too close to the desired fundamental output frequency, thus minimizing the cost of filtering the aliases. Frequency hopping via the PROFILE inputs and associated tuning word is also supported in single-tone mode, which allows frequency shift keying (FSK) modulation.
The AD9877 includes three high speed, high performance ADCs. Two matched 8-bit ADCs are optimized for analog IQ demodulated signals and can be sampled at rates up to 16.5 MSPS. A direct IF 12-bit ADC can sample signals at rates up to 33 MSPS. The ADC sampling frequency can be derived directly from the OSCIN signal or from the on-chip OSCIN multiplier. For highest dynamic performance, it is recommended to choose an OSCIN frequency that can be directly used as the ADC sampling clock. Digital 8-bit ADC outputs are multiplexed to one 4-bit bus, clocked by the master clock (MCLK). The 12-bit ADC uses a nonmultiplexed 12-bit interface with an output data rate of half fMCLK frequency.
REV. A
-15-
AD9877
Clock and Oscillator Circuitry
The AD9877's internal oscillator generates all sampling clocks from a simple, low cost, parallel resonance, fundamental frequency quartz crystal. Figure 2 shows how the quartz crystal is connected between OSCIN (Pin 61) and XTAL (Pin 60) with parallel resonant load capacitors as specified by the crystal manufacturer. The internal oscillator circuitry can also be overdriven by a clock applied to OSCIN with XTAL left unconnected.
An external PLL loop filter (Pin 57) consisting of a series resistor and ceramic capacitor (Figure 2, R1 = 1.3 k, C12 = 0.01 F) is required for stability of the PLL. Also, a shield surrounding these components is recommended to minimize external noise coupling into the PLL's voltage-controlled oscillator input (guard trace connected to AVDDPLL). Figure 1 shows that ADCs are either sampled directly by a low jitter clock at OSCIN or by a clock that is derived from the PLL output. Operating modes can be selected in Register 8. Sampling the ADCs directly with the OSCIN clock requires MCLK to be programmed at twice the OSCIN frequency.
fOSCIN = f MCLC x N M
An internal phase-locked loop (PLL) generates the DAC sampling frequency, fSYSCLK , by multiplying OSCIN frequency M times. The MCLK signal (Pin 23) fMCLK is derived by dividing this PLL output frequency by N (Register Address 01h).
fSCYCLK = fOSCIN x M
f MCLK = fOSCIN x M N
CP1 10 F C1 C2 C3 0.1 F 0.1 F 0.1 F CP2 10 F C4 C5 C6 0.1 F 0.1 F 0.1 F
93 REFB12
94 REFT12
85 REFB8
86 REFT8
99 AGND
96 AGND
91 AGND
88 AGND
83 AGND
95 AVDD
92 AVDD
87 AVDD
84 AVDD
82 Q IN+
100 NC
81 Q IN-
80 AGNDIQ 79 I IN+ 78 I IN- 77 AGNDIQ 76 NC 75 NC 74 AGNDIQ 73 AVDDIQ 72 DRVDD 71 OSCOUT 70 DRGND 69 DGNDSD 68 SDELTA0 67 SDELTA1 66 DVDDSD 65 CA_EN 64 CA_DATA 63 CA_CLK 62 DVDDOSC 61 OSCIN 60 XTAL 59 DGNDOSC 58 AGNDPLL 57 PLLFILTER 56 AVDDPLL 55 DVDDPLL 54 DGNDPLL 53 AVDDTx 52 Tx+ 51 Tx- GUARD TRACE C12 R1 1.3k 0.01 F C10 20pF C11 20pF
98 IF12+
97 IF12-
90 NC SCLK 41
AVDD DRGND DRVDD (MSB) IF(11) IF(10) IF(9) IF(8) IF(7) IF(6)
1 2 3 4 5 6 7 8 9
IF(5) 10 IF(4) 11 IF(3) 12 IF(2) 13 IF(1) 14 IF(0) 15 (MSB) RxIQ(3) 16 RxIQ(2) 17 RxIQ(1) 18 RxIQ(0) 19 RxSYNC 20 DRGND 21 DRVDD 22 MLCK 23 DVDD 24 DGND 25 TxSYNC 26 (MSB) TxIQ(5) 27 TxIQ(4) 28 TxIQ(3) 29 TxIQ(2) 30
AD9877
TOP VIEW (Pins Down)
TxIQ(1) 31
TxIQ(0) 32
DVDD 33
DGND 34
PROFILE(1) 35
PROFILE(0) 36
RESET 37
DVDD 38
DGND 39
DGND 40
CS 42
89 NC
SDIO 43
SDO 44
DGNDTx 45
DVDDTx 46
PWRDN 47
REFIO 48
FSADJ 49
AGNDTx 50
RSET 2k
C13 0.1 F NC = NO CONNECT
Figure 2. Basic Connections Diagram
-16-
REV. A
AD9877
PROGRAMMABLE CLOCK OUTPUT REF CLK
The AD9877 provides a frequency-programmable clock output OSCOUT (Pin 71). OSCIN or MCLK (fMCLK) and the master clock divider ratio R stored in Register Address 01h determine its frequency:
clock cycles after reset. The rising edge of RESET reinitializes the programmable registers to their default values. The same sequence as described in the Power-Up Sequence section should be followed after a reset or change in M. A software reset (writing a 1 into Bit 5 of Register 00) is functionally equivalent to the hardware reset but does not force Register 00 to its default value.
VS
fOSCOUT = f MCLC / R or fOSCIN
In its default setting (0x00 in Register 1), the OSCOUT pin provides a buffered output of fOSCIN.
RESET AND TRANSMIT POWER-DOWN Power-Up Sequence
RESET 1ms PWRDN 5 MCLK
On initial power-up, the RESET pin should be held low until the power supply is stable. Once RESET is de-asserted, the AD9877 can be programmed over the serial port. It is recommended that the PWRDN pin be held low during the reset. Changes to ADC Clock Select (Register 08h) or SYS Clock Divider N (Register 01) should be programmed before the rising edge of PWRDN. Changes to the multiplier (M) will require the PLL to reacquire the new frequency and may take up to 1 ms. Once the PLL is frequency-locked and after the PWRDN pin is brought high, transmit data can be sent reliably. If the PWRDN pin cannot be held low throughout the reset and PLL settling time period, then the Power-Down Digital Tx Bit or the PWRDN pin should be pulsed after the PLL has settled. This will ensure correct transmit filter initialization.
RESET
Figure 3. Power-Up Sequence for Tx Data Path
Transmit Power-Down
A low level on the PWRDN pin stops all clocks linked to the digital transmit data path and resets the CIC filter. De-asserting PWRDN reactivates all clocks. The CIC filter is held in a reset state for 80 MCLK cycles after the rising edge of PWRDN to allow for flushing of the half-band filters with new input data. Transmit data bursts should be padded with at least 20 symbols of null data directly before the PWRDN pin is asserted. Immediately after the PWRDN pin is de-asserted, the transmit burst should start with a minimum of 20 null data symbols. This avoids unintended DAC output samples caused by the transmit path latency and filter settling time. Software Power-Down Digital Tx (Bit 5 in Register 02) is functionally equivalent to the hardware PWRDN pin and takes effect immediately after the last register bit has been written over the serial port.
To initiate hardware reset, the RESET pin should be held low for at least 100 ns. All internally generated clocks but OSCOUT stop during reset. The MCLK signal begins transmission three
PWRDN
5 MCLK 20 NULL SYMBOLS DATA SYMBOLS 0 0 20 NULL SYMBOLS 0 0 0
TxIQ
0
0
0
TxSYNC
Figure 4. Timing Sequence to Flush Tx Data Path
REV. A
-17-
AD9877
SIGMA-DELTA OUTPUTS SERIAL INTERFACE FOR REGISTER CONTROL
The AD9877 contains two independent sigma-delta outputs that provide a digital logic bit stream with an average duty cycle that varies between 0% and 4095/40.96%, depending on the programmed code, as shown in Figure 5.
8 tMCLK 4096 8 tMCLK
000h 001h 002h 800h FFFh 8 tMCLK 4096 8 tMCLK
The AD9877 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9877. Single or multiple byte transfers are supported. Also, the interface can be programmed to read words either MSB first or LSB first. The AD9877's serial interface port I/O can be configured to have one bidirectional I/O (SDIO) pin or two unidirectional I/O (SDIO/SDO) pins.
General Operation of the Serial Interface
Figure 5. Sigma-Delta Output Signals
These bitstreams can be low-pass filtered to generate programmable dc voltages of: VDC = (Sigma - DeltaCode 4096) (VH ) + VL where VH = VDRVDD - 0.6 V and VL = 0.4 V.
AD9877
MCLK 8 CONTROL WORD 1 12 R C DC (0.4 TO DRVDD - 0.6V) SIGMA-DELTA 0 12 R C
There are two phases to a communication cycle with the AD9877. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9877, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9877 serial port controller with information regarding the data transfer cycle, Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9877. The eight remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9877 and the system controller. Phase 2 of the communication cycle is a transfer of 1 to 4 data bytes as determined by the instruction byte. Registers change immediately upon writing to the last bit of each transfer byte.
Instruction Byte
CONTROL WORD 0
DC (0.4 TO DRVDD - 0.6V)
-
The Instruction Byte contains the following information:
MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0
SIGMA-DELTA 1 TYPICAL:
R = 50k C = 0.01 F f-3dB = 1/(2 RC) = 318Hz
Figure 6. Sigma-Delta RC Filter
In cable modem set-top box applications, the outputs can be used to control external variable gain amplifiers and RF tuners. A simple single-pole RC low-pass filter provides sufficient filtering (Figure 6). In more demanding applications where additional gain, level shift, or drive capability is required, a first or second order active filter might be considered for each sigma-delta output (Figure 7).
C
The R/W Bit of the Instruction Byte determines whether a read or a write data transfer will occur after the Instruction Byte write. Logic high indicates a read operation. Logic zero indicates a write operation. The N1:N0 Bits determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in the table below: N1 0 0 1 1 N0 0 1 0 1 Description Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes
AD9877
SIGMA-DELTA R VSD C
R1
R VOUT R OP250 VOUT = (VSD + VOFFSET) (1 + R/R1)/2
VOFFSET TYPICAL: R = 50k C = 0.01 F f-3dB = 1/(2 RC) = 318Hz
The Bits A4:A0 determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9877.
Serial Interface Port Pin Description
Figure 7. Sigma-Delta Active Filter with Gain and Offset
SCLK--Serial Clock. The serial clock pin is used to synchronize data transfers from the AD9877 and to run the serial port state machine. The maximum SCLK frequency is 15 MHz. Input data to the AD9877 is sampled on the rising edge of SCLK. Output data changes on the falling edge of SCLK.
-18-
REV. A
AD9877
CS--Chip Select. Active low input starts and gates a communication cycle. It allows multiple devices to share a common serial port bus. The SDO and SDIO pins go to a high impedance state when CS is high. Chip select should stay low during the entire communication cycle. SDIO--Serial Data I/O. Data is always written into the AD9877 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register 0. The default is logic 0, which configures the SDIO pin as unidirectional. SDO--Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9877 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.
MSB/LSB Transfers
It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset. A write to Bits 1, 2, and 3 of Address 00h with the same logic levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the host processor to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 00h with RESET Bit low and serial port configuration as specified above (XY) reprograms the OSCIN multiplier setting. A changed fSYSCLK frequency is stable after a maximum of 200 fMCLK cycles.
CS SCLK SDIO SDO R/W N1 N0 A4 A3 A2 A1 A0 D7n D6n D7n D6n D20 D10 D00 D20 D10 D00 INSTRUCTION CYCLE DATA TRANSFER CYCLE
The AD9877 serial port can support both the most significant bit (MSB) first or the least significant bit (LSB) first data formats. This functionality is controlled by the LSB first bit in Register 0. The default is MSB first. When this bit is set active high, the AD9877 serial port is in LSB first format. In LSB first mode, the instruction byte and data bytes must be written from the least significant bit to the most significant bit. In LSB first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle. When this bit is set default low, the AD9877 serial port is in MSB first format. In MSB first mode, the instruction byte and data bytes must be written from the most significant bit to the least significant bit. In MSB first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. When incrementing from 0x1F, the address generator changes to 0x00. When decrementing from 0x00, the address generator changes to 0x1F.
Notes on Serial Port Operation
Figure 8a. Serial Register Interface Timing MSB First
CS SCLK SDIO SDO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D00 D10 D20 D6n D7n D6n D7n INSTRUCTION CYCLE DATA TRANSFER CYCLE
Figure 8b. Serial Register Interface Timing LSB First
f SCLK t PWH
SCLK
CS
t DS
t PWL
t DS
SDIO
t DH
INSTRUCTION BIT 6
INSTRUCTION BIT 7
The AD9877 serial port configuration bits reside in Bit 6 and Bit 7 of Register Address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the RESET Bit in Register Address 00h. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 00h.
Figure 9. Timing Diagram for Register WRITE to AD9877
CS
SCLK
t DV
SDIO SDO DATA BIT N DATA BIT N - 1
Figure 10. Timing Diagram for Register READ from AD9877
t SU
MCLK
t HD
TxSYNC
TxIQ
TxI[11:6]
TxI[5:0]
TxQ[11:6]
TxQ[5:0]
TxI[11:6]
TxI[5:0]
TxQ[11:6]
TxQ[5:0]
TxI[11:6]
TxI[5:0]
Figure 11. Transmit Timing Diagram
REV. A
-19-
AD9877
TRANSMIT PATH (TX) Transmit Timing
The transfer function is given by:
The AD9877 provides a master clock MCLK and expects 6-bit multiplexed TxIQ data on each rising edge. Transmit symbols are framed with the TxSYNC input. TxSYNC high indicates the start of a transmit symbol. Four consecutive 6-bit data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB).
Data Assembler
1 sin( f R ) 1 1 - e - j (2 f R ) = H( f ) = R 1 - e- j 2f R sin( f )
3
3
The input data stream is representative complex data. Two 6-bit words form a 12-bit symbol component (two's complement format). Four input samples are required to produce one I/Q data pair. The I/Q sample rate fIQCLK at the input to the first half-band filter is a quarter of the input data rate fMCLK. The I/Q sample rate fIQCLK puts a bandwidth limit on the maximum transmit spectrum. This is the familiar Nyquist limit and is equal to one-half fIQCLK, which hereafter will be referred to as fNYQ.
Half-Band Filters (HBFs)
The frequency response in this form is such that f is scaled to the output sample rate of the CIC filter. That is, f = 1 corresponds to the frequency of the output sample rate of the CIC filter. H(z) will yield the frequency response with respect to the input sample of the CIC filter.
Combined Filter Response
The combined frequency response of HBF 1, HBF 2, and CIC is shown in Figures 12a to 12c and Figures 13a to 13c. The usable bandwidth of the filter chain puts a limit on the maximum data rate that can be propagated through the AD9877. A look at the pass band detail of the combined filter response (Figures 12d and 13d) indicates that in order to maintain an amplitude error of no more than 1 dB, we are restricted to signals having a bandwidth of no more than about 60% of fNYQ. Thus, in order to keep the bandwidth of the data in the flat portion of the filter pass band, the user must oversample the baseband data by at least a factor of 2 prior to representing it to the AD9877. Note that without oversampling, the Nyquist bandwidth of the baseband data corresponds to the fNYQ. As such, the upper end of the data bandwidth will suffer 6 dB or more of attenuation due to the frequency response of the digital filters. Furthermore, if the baseband data applied to the AD9877 has been pulse shaped, there is an additional concern. Typically, pulse shaping is applied to the baseband data via a filter having a raised cosine response. In such cases, an value is used to modify the bandwidth of the data where the value of is such that 0 1. A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to be extended to twice the Nyquist bandwith. Thus, with 2 oversampling of the baseband data and = 1, the Nyquist bandwidth of the data will correspond with the I/Q Nyquist bandwidth. As stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. The maximum value of that can be implemented is 0.45. This is because the data bandwidth becomes: 1 2 (1 + ) f NYQ = 0.725 f NYQ which puts the data bandwidth at the extreme edge of the flat portion of the filter response. If a particular application requires an value between 0.45 and 1, the user must oversample the baseband data by at least a factor of 4. The combined HB1, HB2, and CIC filter introduces, over the frequency range of the data to be transmitted, a worst-case droop of less than 0.2 dB.
HBF 1 and HBF 2 are both interpolating filters, each of which doubles the sampling rate. Together, HBF 1 and HBF 2 have 26 taps and provide a factor of 4 increase in the sampling rate (4 fIQCLK or 8 fNYQ). In relation to phase response, both HBFs are linear phase filters. As such, virtually no phase distortion is introduced within the pass band of the filters. This is an important feature, since phase distortion is generally intolerable in a data transmission system.
Cascaded Integrator-COMB (CIC) Filter
A CIC filter is unlike a typical FIR filter in that it offers the flexibility to handle differing input and output sample rates in any integer ratios. In the AD9877, the CIC filter is configured as a programmable interpolator and provides a sample rate increase by a factor of R = 3 or R = 4. In addition to the ability to provide a change in the sample rate between the input and the output, a CIC filter also has an intrinsic low pass frequency response characteristic. The frequency response of a CIC filter is dependent on three factors: 1. The rate change ratio, R. 2. The order of the filter, n. 3. The number of unit delays per stage, m. It can be shown that the system function H(z) of a CIC filter is given by:
1 Rm -1 1 1 - z - Rm = z-k H(z ) = -1 R k = 0 R 1- z
n
n
The form on the far right has the advantage of providing a result for z = 1 (corresponding to zero frequency or dc). The alternate form yields an indeterminate form (0/0) for z = 1 but is otherwise identical. The only variable parameter for the AD9877's CIC filter is R; m and n are fixed at 1 and 3, respectively. Thus, the CIC system function for the AD9877 simplifies to:
1 R -1 1 1 - z-R = z-k H(z ) = -1 R k = 0 R 1- z
3 3
-20-
REV. A
AD9877
10 0 -10 10 0 -10
MAGNITUDE - dB
-20 -30 -40 -50 -60 -70 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY - fS/2 0.8 0.9 1.0
MAGNITUDE - dB
-20 -30 -40 -50 -60 -70 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY - fS/2 0.8 0.9 1.0
Figure 12a. Cascaded Filter 12x Interpolator (N = 3)
Figure 13a. Cascaded Filter 16x Interpolator (N = 4)
10 0 -10
10 0 -10
MAGNITUDE - dB
-20 -30 -40 -50 -60 -70 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY - fS/2 0.8 0.9 1.0
MAGNITUDE - dB
-20 -30 -40 -50 -60 -70 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY - fS/2 0.8 0.9 1.0
Figure 12b. Input Signal Spectrum (N = 3), = 0.25
Figure 13b. Input Signal Spectrum (N = 4), = 0.25
10 0 -10
MAGNITUDE - dB
10 0 -10
MAGNITUDE - dB
-20 -30 -40 -50 -60 -70 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY - fS/2 0.8 0.9 1.0
-20 -30 -40 -50 -60 -70 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY - fS/2 0.8 0.9 1.0
Figure 12c. Response to Input Signal Spectrum (N = 3)
Figure 13c. Response to Input Signal Spectrum (N = 4)
REV. A
-21-
AD9877
1 1 0 -1 MAGNITUDE - dB -2
MAGNITUDE - dB
0 -1 -2
-3
-3
-4 -5 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY RELATIVE TO I/Q NYQUIST BW 1.0
-4 -5 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY RELATIVE TO I/Q NYQUIST BW 1.0
Figure 12d. Cascaded Filter Pass-Band Detail (N = 3)
Figure 13d. Cascaded Filter Pass-Band Detail (N = 4)
Q
+0.2dB 12 I
Z
-3dB I ATTENUATOR MODULATOR 3dB MAX O I
HBF + CIC INTERPOLATOR
X
I
X
COMPLEX DATA INPUT +0.2dB 12 O HBF + CIC INTERPOLATOR O
-3dB ATTENUATOR
DAC
TWO'S COMPLEMENT FORMAT
Figure 15. Signal Level Contribution Figure 14. 16-Quadrature Modulation
Tx Signal Level Considerations
The following example assumes a Pk/rms level of 10 dB:
(2047 LSBs - 0.2 dB ) = 2000 LSBs Maximum Symbol Component Input Value =
The quadrature modulator itself introduces a maximum gain of 3 dB in the signal level. To visualize this, assume that both the I data and Q data are fixed at the maximum possible digital value, x. Then the output of the modulator, z, is:
z = x cos(t ) - x sin(t )
[
]
It can be shown that z assumes a maximum value of:
z=
(x
2
+ x 2 = x 2 (a gain of +3 dB)
)
2000 LSBs + 6 dB - Pk rms (dB ) = 1265 LSBs rms Maximum Complex Input rms Value calculation uses both I and Q symbol components, which adds a factor of 2 (= 6 dB) to the formula.
Table II shows typical IQ input test signals with amplitude levels related to 12-bit full scale (FS).
Tx Throughput and Latency
Maximum Complex Input rms Value =
However, if the same number of bits were used to represent the z values as is used to represent the x values, an overflow would occur. To prevent this possibility, an effective -3 dB attenuation is internally implemented on the I and Q data path.
z =
(1/ 2 + 1/ 2) = x
Data inputs effect the output fairly quickly but remain effective due to AD9877's filter characteristics. Data transmit latency through the AD9877 is easiest to describe in terms of fSYSCLK clock cycles (4 fMCLK). The numbers quoted are when an effect is first seen after an input value change.
Table II. IQ Input Test Signals
Analog Output Single Tone (fC - f) Single Tone (fC + f) Dual Tone (fC f)
Digital Input I = cos(f) Q = cos(f + 90 ) = -sin(f) I = cos(f) Q = cos(f + 270 ) = +sin(f) I = cos(f) Q = cos(f + 180 ) = -cos(f) or Q = +cos(f)
Input Level FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB
Modulator Output Level FS - 3.0 dB FS - 3.0 dB FS
-22-
REV. A
AD9877
Latency of I/Q data entering the data assembler (AD9877 input) to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles). DC values applied to the data assembler input will take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to propagate and settle at the DAC output. Frequency hopping is accomplished via changing the PROFILE input pins. The time required to switch from one frequency to another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).
D/A Converter
A 12-bit digital-to-analog converter (DAC) is used to convert the digitally processed waveform into an analog signal. The worst-case spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases (please see Analog Devices' DDS Tutorial at www.analog.com/dds). The conversion process will produce aliased components of the fundamental signal at n fSYSCLK fCARRIER (n = 1, 2, and 3). These are typically filtered with an external RLC filter at the DAC output. It is important for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest to avoid modulation impairments. A relatively inexpensive seventh order elliptical low-pass filter is sufficient to suppress the aliased components for HFC network applications. The AD9877 provides true and complement current outputs. The full-scale output current is set by the RSET resistor at Pin 49 and the DAC gain register. Assuming maximum DAC gain, the value of RSET for a particular full-scale IOUT is determined using the following equation:
using a broadband 1:1 transformer. Using a grounded center tap results in signals at the AD9877 DAC output pins that are symmetrical about ground. As previously mentioned, by differentially combining the two signals, the user can provide some degree of common-mode signal rejection. A differential combiner might consist of a transformer or an operational amplifier. The object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable characteristic, such as 60 Hz hum or clock feedthrough that is equally present on both individual signals. Connecting the AD9877 true and complement outputs to the differential inputs of the gain-programmable cable drivers AD8321/AD8323 or AD8322/AD8327 provides an optimized solution for the standard-compliant cable modem upstream channel. The cable driver's gain can be programmed through a direct 3-wire interface using the AD9877's profile registers.
AD832x
DAC Tx CA LOW-PASS FILTER 3 CA_EN CA_DATA CA_CLK
75
AD9877
VARIABLE GAIN CABLE DRIVER AMPLIFIER
Figure 16. Cable Amplifier Connection
8 t MCLK 8 t MCLK 4 t MCLK CA_EN CA_CLK 4 t MCLK 8 t MCLK
RSET = 32 VDACRSET IOUT = 39.4 IOUT
For example, if a full-scale output current of 20 mA is desired, then RSET = (39.4/0.02) or approximately 2 k . The following equation calculates the full-scale output current, including the programmable DAC gain control.
IOUT = 39.4 RSET x 10 ( -7.5 + 0.5NGAIN ) 20
[
]
(
)
CA_DATA
MSB
LSB
Figure 17. Cable Amplifier Interface Timing
PROGRAMMING THE AD8321/AD8325 OR AD8322/AD8327 CABLE DRIVER AMPLIFIER GAIN CONTROL
Where NGAIN is the value of DAC Fine Gain Control[3:0]. The full-scale output current range of the AD9877 is 4 to 20 mA. Full-scale output currents outside of this range will degrade SFDR performance. SFDR is also slightly affected by output matching, that is, the two outputs should be terminated equally for best SFDR performance. The output load should be located as close as possible to the AD9877 package to minimize stray capacitance and inductance. The load may be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer-coupled circuit. It is best not to attempt to directly drive highly reactive loads (such as an LC filter). Driving an LC filter without a transformer requires that the filter be doubly terminated for best performance, that is, the filter input and output should both be resistively terminated with the appropriate values. The parallel combination of the two terminations will determine the load that the AD9877 will see for signals within the filter pass band. For example, a 50 terminated input/output low-pass filter will look like a 25 load to the AD9877. The output compliance voltage of the AD9877 is -0.5 V to +1.5 V. Any signal developed at the DAC output should not exceed 1.5 V, otherwise signal distortion will result. Furthermore, the signal may extend below ground as much as 0.5 V without damage or signal distortion. The AD9877 true and complement outputs can be differentially combined for common-mode rejection REV. A
Programming the gain of the AD832x family cable driver amplifier can be accomplished via the AD9877 cable amplifier control interface. Four 8-bit registers within the AD9877 (one per profile) store the gain value to be written to the serial 3-wire port. Typically either AD8321/AD8325 or AD8322/AD8327 variable gain cable amplifiers are connected to the chip's 3-wire cable amplifier interface. The Tx Gain Control Select Bit in Register 0F changes the interpretation of the bits in Registers 13, 17, 1B, and 1F. (see Cable Driver Gain Control Register description). Data transfers to the gain-programmable cable driver amplifier are initiated by four conditions. Each is described below: 1. Power-Up and Hardware Reset--Upon initial power-up and every hardware reset, the AD9877 clears the contents of the gain control registers to 0, which defines the lowest gain setting of the AD832x. Thus, the AD9877 writes all 0s out of the 3-wire cable amplifier control interface. 2. Software Reset--Writing a 1 to Bit 5 of Address 00 initiates a software reset. On a software reset, the AD9877 clears the contents of the gain control registers to 0 for the lowest gain and sets the profile select to 0. The AD9877 writes all 0s out of the 3-wire cable amplifier control interface if the gain was on a different setting (different from 0) before. -23-
AD9877
3. Change in Profile Selection--The AD9877 samples the PROFILE[1] and PROFILE[2] input pins together with the two profile select bits and writes to the AD832x gain control registers if a change in profile and gain is determined. The data written to the cable driver amplifier comes from the AD9877 gain control register associated with the current profile. 4. Write to AD9877 Cable Driver Amplifier Control Registers-- The AD9877 will write gain control data associated with the current profile to the AD832x whenever the selected AD9877 cable driver amplifier gain setting is changed. Once a new stable gain value has been detected (48 MCLK to 64 MCLK cycles after initiation) data write starts with CA_CS going low. The AD9877 will always finish a write sequence to the cable driver amplifier once it is started. The logic controlling data transfers to the cable driver amplifier uses up to 200 MCLK cycles and has been designed to prevent erroneous write cycles from ever occurring.
RECEIVE PATH (Rx) ADC Theory of Operation
The digital data outputs of the ADCs are represented in straight binary format. They saturate to full scale or zero when the input signal exceeds the input voltage range.
Receive Timing
The AD9877 sends multiplexed data to the RxIQ outputs on every rising edge of MCLK. The data stream consists of two nibbles of I data followed by two nibbles of Q data. The RxSYNC pulse frames the I/Q data and is high coincidentally with the most significant nibble of the I data-word. If the 8-bit I/Q ADC is in power-down mode, the RxSYNC signal will not be generated. The 12-bit ADC data is sent to the IF[11:0] outputs on every second falling edge of MCLK. In its default setting, the OSCOUT pin provides a buffered version of fOSCIN. OSCOUT can be used as a qualifying clock for the Rx data when the ratio between OSCIN multiplier and OSCIN divider is programmed to be 2 (M/N = 2) or when the ADC sampling is selected to be derived from fOSCIN directly.
Driving the Analog Inputs
The AD9877's analog-to-digital converters implement pipelined multistage architectures to achieve high sample rates while consuming low power. Each ADC distributes the conversion over several smaller ADC subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, ADCs require a small fraction of the 2n comparators used in a traditional n-bit flash-type ADC. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
AINP AINN SHA A/D D/A SHA A/D D/A GAIN A/D
Figure 19 illustrates the equivalent analog inputs of the AD9877 (a switched capacitor input). Bringing CLK to a logic high opens Switch S3 and closes Switches S1 and S2. The input source is connected to AIN and must charge capacitor CH during this time. Bringing CLK to a logic low opens S2, and then Switch S1 opens followed by closing S3. This puts the input in the hold mode.
AD9877
AINP 2k VBIAS 2k AINN CP CP S3 CH S2 S1 CH
Figure 19. Differential Input Architecture
AD9877
CORRECTION LOGIC
Figure 18. ADC Architecture
The analog inputs of the AD9877 incorporate a novel structure that merges the input sample-and-hold amplifiers (SHA) and the first pipeline residue amplifiers into single, compact switched capacitor circuits. This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. By matching the sampling network of the input SHA with the first stage flash ADC, the ADCs can sample inputs well beyond the Nyquist frequency with no degradation in performance.
The structure of the input SHA places certain requirements on the input drive source. The combination of the pin capacitance and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to its n-bit accuracy in one-half of a clock cycle. When the SHA goes into track mode, the input source must charge or discharge capacitor CH from the voltage already stored on CH to the new voltage. In the worst case, a full-scale voltage step on the input source must provide the charging current through the RON (100 ) of Switch S1 and quickly (within 1/2 CLK period) settle. This situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously stored on CH, the hold capacitor requires no input current and the equivalent input impedance is extremely high. Adding series resistance between the output of the signal source and the AIN pin reduces the drive requirements placed on the signal source. Figure 20 shows this configuration.
-24-
REV. A
AD9877
<50 VS <50 AINN SHUNT AINP
An improvement in THD and SFDR performance can be realized by operating the AD9877 in differential mode. The performance enhancement between the differential and single-ended mode is most considerable as the input frequency approaches and goes beyond the Nyquist frequency (i.e., fIN > fS/2). The AD8131 provides a convenient method of converting a single-ended signal to a differential signal. This is an ideal method for generating a direct coupled signal to the AD9877. The AD8131 will accept a signal swinging below 0 V and shift it to an externally provided common-mode voltage. The AD8131 configuration is shown in Figure 21.
Figure 20. Simple ADC Drive Configuration
The bandwidth of the particular application limits the size of this resistor. To maintain the performance outlined in the data sheet specifications, the resistor should be limited to 50 or less. For applications with signal bandwidths less than 10 MHz, the user may proportionally increase the size of the series resistor. Alternatively, adding a shunt capacitance between the AIN pins can lower the ac load impedance. The value of this capacitance will depend on the source resistance and the required signal bandwidth. In systems that must use dc-coupling, use an op amp to comply with the input requirements of the AD9877.
Op Amp Selection Guide
SINGLE-ENDED ANALOG INPUT
R1 AD8131 R1
R2
AD9877
AINP
R2
AINN
Op amp selection for the AD9877 is highly application dependent. In general, the performance requirements of any given application can be characterized by either time domain or frequency domain constraints. In either case, one should carefully select an op amp that preserves the performance of the ADC. This task becomes challenging when one considers the AD9877's high performance capabilities coupled with other system level requirements, such as power consumption and cost. The ability to select the optimal op amp may be further complicated by either limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high performance op amps typically have input and output range limitations in accordance with their lower supply voltages. As a result, some op amps will be more appropriate in systems where ac-coupling is allowed. When dc-coupling is required, op amp headroom constraints (such as rail-to-rail op amps), or ones where larger supplies can be used, should be considered. Analog Devices offers differential output operational amplifiers, such as the AD8131, with a fixed gain of 2. It can be used for differential or single-ended-to-differential signal conditioning with 8-bit performance to directly drive ADC inputs. The AD8138 is a higher performance version of the AD8131. It provides 12-bit performance and allows different gain settings. Please contact the factory or local sales office for updates on Analog Devices' latest amplifier product offerings.
ADC Differential Inputs
Figure 21. Single-Ended-to-Differential Input Drive
Figure 22 shows the schematic of a possible transformer coupled circuit. Transformers with turn ratios (n2/n1) other than 1 may be selected to optimize the performance of a given application. For example, selecting a transformer with a higher impedance ratio (e.g., minicircuits T16-6T with an impedance ratio of (z2/z1) = 16 = (n2/n1)2) effectively "steps up" the signal amplitude, thus further reducing the output voltage swing of the signal source. In Figure 22, a resistor R1 is added between the analog inputs to match the source impedance R as in the formula:
R = R1 RAIN
[
] (Z
1
Z2 )
R C R1
AD9877
AINP
AINN
Figure 22. Transformer Coupled Input
ADC Voltage References
The AD9877 uses a 1 V p-p input span for the 8-bit ADC inputs and a 2 V p-p for the 12-bit ADC. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. In systems that do not need a dc input, an RF transformer with a center tap is the best method to generate differential inputs beyond 20 MHz for the AD9877. This provides all the benefits of operating the ADC in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the ADC.
The AD9877 has two independent internal references for its 8-bit and 12-bit ADCs. Both 8-bit ADCs have a 1 V p-p input and share one internal reference source. The 12-bit ADC, however, is designed for 2 V p-p input voltages and provides its own internal reference. Figure 2 shows the proper connections of the reference pins REFT and REFB. External references may be necessary for systems that require high accuracy gain matching between ADCs or improvements in temperature drift and noise characteristics. External references REFT and REFB need to be centered at AVDD/2 with offset voltages as specified: REFT8: AVDDIQ/2 + 0.25 V, REFB8: AVDDIQ/2 - 0.25 V REFT12: AVDD/2 + 0.5 V, REFB12: AVDD/2 - 0.5 V
REV. A
-25-
AD9877
A differential level of 0.5 V between the reference pins results in a 1 V p-p ADC input level AIN. A differential level of 1 V between the reference pins results in a 2 V p-p ADC input level AIN. Internal reference sources can be powered down when external references are used (Register Address 02).
PCB DESIGN CONSIDERATIONS
currents on the power plane and should be kept the furthest from the MxFE and analog sections of the board. The DVDD portion of the plane brings the current used to power the digital portion of the MxFE to the device. This should be treated similarly to the 3 VDD power plane and be kept from going underneath the MxFE or analog components. The MxFE should largely sit above the AVDD portion of the power plane. The AVDD and DVDD power planes may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the DVDD portion of the MxFE from corrupting the AVDD supply. This can be done by using ferrite beads between the voltage source and DVDD and between the source and AVDD. Both DVDD and AVDD should have a low ESR, bulk decoupling capacitor on the MxFE side of the ferrite as well as low ESR, ESL decoupling capacitors on each supply pin (i.e., the AD9877 requires 17 power supply decoupling caps). The decoupling caps should be placed as close to the MxFE supply pins as possible. An example of the proper decoupling is shown in the AD9877 evaluation board schematic.
Ground Planes
Although the AD9877 is a mixed-signal device, the part should be treated as an analog component. The digital circuitry on-chip has been specially designed to minimize the impact that the digital switching noise will have on the operation of the analog circuits. Following the power, grounding, and layout recommendations in this section will help you get the best performance from the MxFE.
Component Placement
If the three following guidelines of component placement are followed, chances for getting the best performance from the MxFE are greatly increased. First, manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the MxFE or analog circuits. Second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. Third, keep digital (noise generating) and analog (noise susceptible) circuits as far away from each other as possible. In order to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. This will keep the highest frequency return current paths short and prevent them from traveling over the sensitive MxFE and analog portions of the ground plane. Also, these circuits should be generously bypassed at each device, which will further reduce the high frequency ground currents. The MxFE should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections will not flow in the ground plane under the MxFE. The analog circuits should be placed furthest from the power supply. The AD9877 has several pins that are used to decouple sensitive internal nodes. These pins are REFIO, REFB8, REFT8, REFB12, and REFT12. The decoupling capacitors connected to these points should have low ESR and ESL. These capacitors should be placed as close to the MxFE as possible and be connected directly to the analog ground plane. The resistor connected to the FSADJ pin and the RC network connected to the PLLFILT pin should also be placed close to the device and connected directly to the analog ground plane.
Power Planes and Decoupling
In general, if the component placing guidelines discussed earlier can be implemented, it is best to have at least one continuous ground plane for the entire board. All ground connections should be made as short as possible. This will result in the lowest impedance return paths and the quietest ground connections. If the components cannot be placed in a manner which would keep the high frequency ground currents from traversing under the MxFE and analog components, it may be necessary to put current-steering channels into the ground plane to route the high frequency currents around these sensitive areas. These currentsteering channels should be made only when and where necessary.
Signal Routing
The digital Rx and Tx signal paths should be kept as short as possible. Also, the impedance of these traces should have a controlled impedance of about 50 . This will prevent poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. If the signal traces cannot be kept shorter than about 1.5 in., then series termination resistors (33 to 47 ) should be placed close to all signal sources. It is a good idea to series terminate all clock signals at their source regardless of trace length. The receive (I IN, Q IN, and RF IN) signals are the most sensitive signals on the entire board. Careful routing of these signals is essential for good receive path performance. The Rx signals form a differential pair and should be routed together as a pair. By keeping the traces adjacent to each other, noise coupled onto the signals will appear as common mode and will be largely rejected by the MxFE receive input. Keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the MxFE will further reduce the possibility of noise corrupting these signals.
The AD9877 evaluation board demonstrates a good power supply distribution and decoupling strategy. The board has four layers: two signal layers, one ground plane, and one power plane. The power plane is split into a 3 VDD section used for the 3 V analog supply pins of the AD9877 and a VANLG section that supplies the higher voltage analog components on the board. That 3 VDD section will typically have the highest frequency
-26-
REV. A
AD9877
OUTLINE DIMENSIONS 100-Lead Plastic Quad Flatpack [MQFP] (S-100C)
Dimensions shown in millimeters
23.20 BSC
20.00 BSC 3.40 MAX
80 81
18.85 REF
51 50
12.35 REF
TOP VIEW
(PINS DOWN)
14.00 BSC 17.20 BSC
PIN 1 100 1 30 31
0.65 BSC
0.40 0.22
2.90 2.70 2.50
1.03 0.88 0.73
SEATING PLANE
0.13 COPLANARITY
0.50 0.25
COMPLIANT TO JEDEC STANDARDS MS-022-GC-1
Revision History
Location 7/02--Data Sheet changed from REV. 0 to REV. A. Page
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to RESET AND TRANSMIT POWERDOWN section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REV. A
-27-
-28-
C02952-0-7/02(A)
PRINTED IN U.S.A.

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